1. Field of the Invention
This invention relates to a memory device such as a semiconductor memory device, and specifically concerns a memory device that prevents the slowing of read operation through use of a mask signal used during burst write mode.
2. Description of the Related Art
Memory devices such as recent semiconductor memory devices have a burst mode that accesses memory cells of differing columns in a state with word lines selected by row addresses being driven. By using this burst mode, it is possible to read multiple read data at high speed in a short period of time, or to write multiple write data at high speed in a short period of time.
On the other hand, for this burst mode for which high speed access is possible, to make it possible to prevent reading or writing of specific data, an input/output mask signal (DQ mask) is used. Specifically, in the burst mode, when read or write is performed in succession synchronous with the clock, an input/output mask signal is allocated at the timing of a preset read or write number, and the write operation at the time of mask signal and the read operation at 2 clocks later from the mask signal is prohibited.
Generally, with memory devices, a bit line selected from multiple bit lines is connected to a common data bus by a column selection signal, read is performed from the main amplifier for reading which is installed in the data bus, or write is performed from the write amplifier also installed in the data bus. Therefore, to prohibit read or write using the aforementioned I/O mask signal, it is necessary to drive the column selection signal in response to the I/O mask signal.
FIG. 1 is a schematic diagram of part of a prior memory device. In this schematic diagram, mainly column side circuits and I/O parts are shown, and row circuits are omitted. Sense amplifier SA is installed adjacent to memory cell array MCA. In the diagram, the double square represents an external terminal, and external terminals for addresses A00 to Axx, I/O terminal DQ, clock CLK, and I/O mask DQM are shown. Addresses A00 to Axx are allocated to predecoder 14, and column selection signals CL0 to CL255 are generated by column decoder 16. Furthermore, column selection signal CL is generated synchronous with clock CLK.
Sense amplifier SA detects the electric potential of bit lines (not illustrated), and outputs read data to read data bus rdb in response to column selection signal CL. The read data of read data bus rdb is amplified by main amplifier 20 and output to I/O terminal DQ. On the other hand, write data is supplied from I/O terminal DQ and sent to write data bus wdb by write amplifier 18. Then, write data bus wdb is connected to the bit line (not illustrated) selected by column selection signal CL. As a result, data is written to a memory cell.
Furthermore, in order to put column selection signal CL in a non-select state in response to I/O mask signal DQM supplied from outside, logic circuit 30 is installed. This logic circuit 30 is controlled so that column selection signal CL is generated synchronous with the clock CLK timing while the generation of column selection signal CL is prohibited in response to the status of I/O mask signal DQM.
FIG. 2 is a burst write operation timing chart diagram for the memory device shown in FIG. 1. This example shows a 4-bit burst write mode. The write mode is synchronous with the rising edge of clock CLK at time t1, and during the four clock cycles thereafter, four write data are supplied. Column selection signals CL are generated successively synchronously with this. However, in response to I/O mask signal DQM supplied at the second clock cycle, generation of column selection signal CL is prohibited. As a result, data write of the second clock cycle is prohibited.
We must note that with the aforementioned memory device, there is a problem of read operation being slow. For memory devices, requests for acceleration of reading are generally greater than for writing. With the read operation of the aforementioned memory device, sense amplifier SA operates after a word line is driven, the column address is decoded and column selection signal CL is generated, the read data of sense amplifier SA is output to main amplifier 20, and data is output from I/O terminal DQ. Therefore, performing generation of the column selection signal CL as quickly as possible is necessary to increase the read speed.
As shown in FIG. 1, critical path 32 for generating this column selection signal CL passes from clock CLK through logic circuit 30, predecoder 14, and column decoder 16. Reducing the delay time of this critical path as much as possible makes it possible to accelerate the read operation.
However, as mentioned above, there is a logic operation with the status of I/O mask signal DQM in critical path 32, so it is not possible to sufficiently accelerate the generation of column selection signal CL.